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ST
ST3005
Speech Decoder/Encoder
Notice: Sitronix Technology Corp. reserves the right to change the contents in this document without prior notice. This is not a final specification. Some parameters are subject to change.
1. FEATURES
n n DSP based voice/audio processor Operation voltage - Core logic: 2.25V~2.7V - I/O pads: 3.0V~3.6V Voltage regulator for core logic Low Voltage Reset (LVR) _ 2.5V low voltage reset One PLL to generate high system frequency from a 4MHz source _ 12M~28MHz PLL output Triple clock sources _ Crystal...........................................................4MHz _ External input...... ... ... ... ... ... ... ... ... ... ... ......4MHz Low power down current _Typical current: 3uA One 16-bit programmable Timer One clocking output One external interrupt _ Edge/level trigger supported One 14-bit direct-drive DAC - Maximum current: 145mA n MCU interfaces _ Serial mode _ Parallel mode Two Serial PORT interfaces(SP) _ Programmable data length from 8-bit to 16-bit _ I2S, Left/Right Justified interfaces to external DAC/ADC Speech playback/recorder _ Low Bit Rate Compression (LBRC) _ 1.2K/1.6K/2.4Kbps@8KHz playback _ 1.6K/2.2K/3.3Kbps@11.025KHz playback _ Middle Bit Rate Compression (MBRC) _ 5.4K/6.4Kbps@8KHz playback _ 7.4K/8.8Kbps@11.025KHz playback _ High Bit Rate Compression (HBRC) _ 12K/16K/24Kbps@8KHz playback _ 16.5K/22K/33Kbps@11.025KHz playback _ 24K/32K/48Kbps@16KHz playback _ 12k/16k/24kbps@8KHz encoder _ PCM playback _ Time stretch (half~double speed)
n
n n n
n
n
n n n n n
2. GENERAL DESCRIPTION
The ST3005 is a highly integrated and cost-effective DSP based audio processor for various consumer applications. It consists of one powerful DSP for advanced voice decoder and encoder algorithms of natural speech with less memory. It provides low bit rate compression (LBRC) and middle bit rate (MBRC) for voice playback and high bit rate compression (HBRC) for audio or better voice quality. Both LBRC/MBRC and HBRC can playback simultaneously. For encoder, it has capability to compress PCM raw data from MCU and send back encoded data to MCU. ST3005 can adjust playback frequency (half~double speed) without pitch shifting. System clock comes from 4MHz crystal or external input. ST3005 has 32 I/Os and these can be either GPIO or functional pins. Each pin can be programmed to input or output. One external interrupt pin can be requested by external devices. One internal 14bit DAC can provide significant volume equipping with internal amplifier. For particular application or recorder, two general audio interfaces are supported to interface with external DAC/ADC. Audio interface can be configured to I2S or Left/Right Justified compatible mode. There are serial and parallel interfaces for various connections with different MCUs.
Ver 0.8
1/11
2007-06-12
ST3005
2.1 Block Diagram
Figure 2-1
ST3005 Block Diagram
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ST3005
3. SIGNAL DESCRIPTIONS
Table 3-1
Function Group Pin Name RESET PWD PWDA OSCXI System control OSXO ECLK CMODE[1:0] TEST[2:0] SO[1:0]/ DPA[7,15] CLKO/ DPA[6] DAP[13,14], DPB[0:15] XREQ/DPA[5] TF0/DPA[0] RF0/DPA[1] TX0/DPA[2] RX0/DPA[3] SCLK0/DPA[4] TF1/DPA[8] RF1/DPA[9] TX1/DPA[10] RX1/DPA[11] SCLK1/DPA[12] D[0]/SCL D[1]/SDI D[2]/SDO D[3:7] WR RD CS Pin # 1 1 1 1 1 1 2 3 2 1 18 1 1 1 1 1 1 1 1 1 1 1 1 1 1 5 1 1 1 I/O I I O I O I I I O O I/O I O I O I O O I O I O I/O I/O I/O I/O I I I
Signal Function Description
Description System reset, low active Power down, low active Power down acknowledge, high active Crystal input or R-oscillator input. If not used, it connects to GND Crystal output. If not used, it connects to GND External clock input. If not used, it connects to GND Clock source select 01=Crystal. ECLK connects to GND 1X=ECLK. OSCXI and OSXO connect to GND Test mode. TEST[2:0] connect to GND SO0/DPA[7], SO1/DPA[15] Clock output/DPA[6] General I/O External interrupt/DPA[5] Transmit frame synchronization/DPA[0] Receive frame synchronization/DPA[1] Serial data transmit/DPA[2] Serial data receive/DPA[3] Serial clock/DPA[4] Transmit frame synchronization/DPA[8] Receive frame synchronization/DPA[9] Serial data transmit/DPA[10] Serial data receive/DPA[11] Serial clock/DPA[12] Parallel : Data bus Serial : Serial clock Parallel : Data bus Serial : Serial data input Parallel : Data bus Serial : Serial data output Parallel : Data bus Serial : Not used Parallel : Write enable, low active Serial : Not used Parallel : Read enable, low active Serial : Not used Parallel : Chip select, low active Serial : Chip select Parallel : Command/data select "H" Data : "L" Command : Serial : Not used
3/11 2007-06-12
Special I/O
GPIO External Interrupt Serial Port0/ DPA[4:0]
Serial Port1/ DPA[12:8]
MCU Interface
CMD
1
I
Ver 0.8
ST3005
REQ RDY PMODE 1 1 1 O O I DSP wants to sent command to MCU, low active DSP permit MCU access data, low active, not used Parallel interface select 0: Parallel (default). Connecting to GND 1: Not used Parallel/serial interface select 0: Serial 1: Parallel 2.5V power 2.5V power ground 3.3V power 3.3V power ground Digital power input of regulator Digital power ground of regulator Digital power input of PLL Digital power ground of PLL Analog power input of PLL Analog power ground of PLL Analog power input of DAC Analog power ground of DAC Analog power input of DAC output stage Analog power ground of DAC output stage 2.5V output of regulator Voltage reference DAC direct drive pin(+) DAC direct drive pin(-) Common mode voltage reference
P/S VDD25 VSS25 VDD33 VSS33 REGVDD33 REGVSS33 PLLVDD25 PLLVSS25 PLLVDD25A PLLVSS25A DACVDD33A DACVSS33A DACOVDD33A DACOVSS33A VCCOUT VREF DACO DACOB VCM
1 2 2 2 2 1 1 1 1 1 1 1 1 2 2 1 1 2 2 1
I I I I I I I I I I I I I I I O O O O O
Power
Regulator DAC
Ver 0.8
4/11
2007-06-12
ST3005
4. ELECTRICAL CHARACTERISTICS
4.1 Absolute Maximum Rations
DC Supply Voltage: VDD33 ---------------- -0.3V to +4.5V Operating Ambient Temperature --------- -10C to +60C Storage Temperature ------------------------ -10C to +125C
*Note: Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device. All the ranges are stress ratings only. Functional operation of this device at these or any other conditions above those indicated in the operational sections of this specification is not implied or intended. Exposed to the absolute maximum rating conditions for extended periods may affect device reliability.
4.2 DC Electrical Characteristics
Table 4-1 DC Electrical Characteristics
Standard operation conditions: VDD33 = 3.3V, GND = 0V, TA = 25C, unless otherwise specified Parameter Operating Voltage Operating Voltage Operating Current Power Down Current Output driving Output sinking Input low voltage Input high voltage Pull-up resistor Pull-down resistor Low Voltage Reset Level Symbol VDD33 VDD25 IOP1 IPD Iod Ios V IL VIH RPU R PD VLVR 2.4 Min. 3.0 2.25 2.5 30 3 16 26 0.6 1.3 54 50 2.5 2.6 4.5 Typ. Max. 3.6 2.7 Unit V V mA mA mA mA V V K K V Run at 24MHz without speaker Condition
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ST3005
4.3 AC Electrical Characteristics
Figure 4-1
Serial Interface Timing Diagram
Figure 4-2
Parallel Interface Timing Diagram
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ST3005
Table 4-2 Symbol
tCSS tCYC tDS tDH tDD
Timing parameters for 0 Rating Typ. Unit
nS nS nS nS 10 nS
Standard operation conditions: VDD33 = 3.3V, GND = 0V, TA = 25C
Characteristic
CS low to 1 SCL rising SCL cycle time Data valid prior SCL falling Data Hold time after SCL rising SDO output delay from SCL falling
st
Min.
100 200 0 10
Max.
Table 4-3 Symbol
tCH tCS tCYC tCCLW tCCHW tCCLR tCCHR tDS tDH tACC tOH
Timing parameters for 0 Rating Typ. Unit
nS nS nS nS nS nS nS nS nS 25 4 nS nS
Standard operation conditions: VDD33 = 3.3V, GND = 0V, TA = 25C
Characteristic
Cmd pin hold time Cmd pin setup time System cycle time Write pulse width Enable H write width Read pulse width Enable H read width Write data setup time Write data hold time Read access time Read data disable time
Min.
5 5 3.5D 0.5D 3D 0.5D 3D 0.5D 5
Max.
Remark: D = time of one DSP system clock
Ver 0.8
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2007-06-12
ST3005
5. PAD DIAGRAM
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ST3005
6. DEVICE INFORMATION
1. Substrate: GND
PAD Symbol No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 TF0 RF0 TX0 RX0 SCLK0 XREQ CLKO SO0 TF1 RF1 TX1 RX1 SCLK1 DPA13 DPA14 SO1 VDD25 VSS25 TEST2 TEST1 TEST0 VSS33 VDD33 DPB0 DPB1 DPB2 DPB3 DPB4 DPB5 DPB6
X 1616.23 1716.23 1816.23 1916.23 2016.23 2116.23 2216.23 2316.23 2416.23 2516.23 2616.23 2716.23 2826.23 2936.23 2977.5 2977.5 2977.5 2977.5 2977.5 2977.5 2977.5 2977.5 2977.5 2977.5 2977.5 2977.5 2977.5 2977.5 2977.5 2977.5
Y 62.5 62.5 62.5 62.5 62.5 62.5 62.5 62.5 62.5 62.5 62.5 62.5 62.5 62.5 406.55 516.55 626.55 736.55 836.55 936.55 1036.55 1136.55 1236.55 1336.55 1436.55 1536.55 1636.55 1736.55 1836.55 1936.55
PAD Symbol No. 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 DPB7 DPB8 DPB9 DPB10 DPB11 DPB12 DPB13 DPB14 DPB15 VSS33 VDD33 PWDA PWD D7 D6 D5 D4 D3 SDO SDI SCL VDD25 VSS25 CMD PMODE REQ RDY WR RD CS
X 2977.5 2977.5 2977.5 2977.5 2977.5 2977.5 2977.5 2977.5 2940 2830 2720 2620 2520 2420 2320 2220 2120 2020 1920 1820 1720 1620 1520 1420 1320 1220 1120 1020 920 820
Y 2036.55 2136.55 2236.55 2336.55 2436.55 2546.55 2656.55 2766.55 3107.5 3107.5 3107.5 3107.5 3107.5 3107.5 3107.5 3107.5 3107.5 3107.5 3107.5 3107.5 3107.5 3107.5 3107.5 3107.5 3107.5 3107.5 3107.5 3107.5 3107.5 3107.5
PAD No. 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
Symbol P/S RESET CMODE0 CMODE1 OSCXI OSXO ECLK VREF VCCOUT REGVDD33 REGVSS33 PLLVSS25 PLLVDD25 PLLVSS25A PLLVDD25A DACVSS33A DACVDD33A VCM DACOB DACOB
X 720 620 520 420 320 210 100 62.5 62.5 62.5 62.5 62.5 62.5 62.5 62.5 62.5 62.5 62.5 62.5 62.5
Y 3107.5 3107.5 3107.5 3107.5 3107.5 3107.5 3107.5 2753.04 2643.04 2533.04 2433.04 2257.04 2157.04 2057.04 1957.04 1781.04 1681.04 1581.04 1481.04 1381.04 1281.04 1081.04 981.04 881.04 781.04
81 DACOVSS33A 62.5 83 DACOVDD33A 62.5 84 DACOVDD33A 62.5 85 86 DACO DACO 62.5 62.5
82 DACOVSS33A 62.51 1181.04
Ver 0.8
9/11
2007-06-12
ST3005
7. APPLICATION CIRCUIT
Figure 7-1
Note:
Application Circuit Diagram
1. 47uF capacitor must be close to DACOVDD33A and DACOVSS33A. 2. If any of OSCXI, OSXO, and ECLK is not used, it needs to connect to GND. 3. The cascade resistor and parallel capacitor on CMD, RD, WR, and CS pins can reduce noise interference. In general, resistor is short and capacitor is open. Please preserve the options on PCB. 4. R2 resistor can adjust headphone volume.
Ver 0.8
10/11
2007-06-12
ST3005
8. REVISION
REVISION
0.1
DESCRIPTION
First release 1. Change PLL maximum output from 36MHz to 32MHz 2. Revise HBRC 11.025kHz playback bps value 3. Add 12k/16k/24kbps@8KHz encoder 4. A drawback of using R-oscillator clock is described 5. Add DC Electrical Characteristics 6. Remove VREF, CLICK, IREF capacitor 7. Revise R-oscillator voltage from VDD33 to VDD25, revise R resistor from 100kOhn to 97kOhm, remove 100pF capacitor 8. Wire SO1 and PWD pins 9. PMODE shorts to GND 10. Relocate RDY pin from MCU parallel and serial interface 1. Add MBRC 2. Modify DAC driving capacity 3. Change IREF to DACVDD33A, change CLICK to DACVSS33A 4. Rename DACVDD33A to DACOVDD33A, rename DACVSS33A to DACOVSS33A 1. TEST[2:0] wire to GND 2. WR, RD cascade 120 Ohm and parallel 10p capacitor 3. ECLK cascade 100 Ohm to low noise 4. Remove R-Oscillator function 1. System low voltage changes from 2.7V to 3.0V 2. The resistor in RD/WR changes from 120Ohm to 220Ohm 1. Change PLL output frequency from 32MH to 28MHz 2. Add inductor and capacitor before power input, revise regulator output capacitor, DACVDD33A and DACOVDD33A power come from battery, add 4MHz crystal label 1. Add CMODE, ECLK, TEST pins descriptions 2. Revise PMODE pin parallel interface select description 3. Revise output driving/sinking, input low/high, and input pull-up/pull-down resistor DC electrical characteristics 4. Revise Read access time from 10ns to 25ns 5. Remove external DAC/ADC block, DC2DC block. Add headphone jack and CMD pin cascade resistor and parallel capacitor. Revise DAC power circuit. Add note item 2 to 4 1. Revise parallel interface timing diagram(CWD pin change to CMD Pin) 2. Application circuit diagram Add parallel capacitor and cascade resistor circuit on CS pin
PAGE
1 1 1 1 1,5 10 10 10 10 10 1 1 2,4,8,9,10 2,4,8,9,10 1 10 10 1,3,10 1 10 1 10
DATE
2005/03/15
0.2
2005/05/12
0.3
2005/06/28
0.4
2005/0705
0.5
2005/08/02
0.6
2005/09/05
3 4 5 7 10 2006/03/17
0.7
0.8
6 10
2006/04/25
The above information is the exclusive intellectual property of Sitronix Technology Corp. and shall not be disclosed, distributed or reproduced without permission from Sitronix. Sitronix Technology Corp. reserves the right to change this document without prior notice and makes no warranty for any errors which may appear in this document. Sitronix products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where products failure could result in injury, or loss of life, or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply. Ver 0.8 11/11 2007-06-12

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